A dynamic random access memory (DRAM) cell is implemented using a number of memory cells formed as part of a large array in a semiconductor chip. The memory cells typically comprise a storage capacitor in combination with an access transistor. A stacked DRAM cell is formed by a stacked capacitor structure which lies on the surface of a semiconductor. An underlying drain/source region from an access transistor is coupled to the stacked transistor""s bottom electrode by a conductive plug which extends from the bottom electrode to an underlying drain/source region of the access transistor.
Typically, the conductive plug is separated from the bottom electrode by a diffusion barrier. For instance, U.S. Pat. No. 5,825,609 (hereinafter referred to as ""609) to Andricacos et al. discloses such a structure at column 6, lines 58-60. This patent also describes a number of layered electrode structures generally connected together by conductive sidewall coatings. Andriacacos further discloses that the conductive plug structure can be entirely filled with one or more barrier materials. However, the complexity of the layered and conductive sidewall-coated structures generally are not well suited for small capacitors which are associated with 1 gigabit or higher memories.